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? 2014 microchip technology inc. ds00001769a-page 1 product features 3.3v operation acpi compliant lpc interface - lpc i/o and trusted cycles decoded vtr (standby) and vbat (power planes) - low standby current in sleep mode configuration register set - compatible with isa plug-and-play standard - ec-programmable base address arc-625d embedded controller (ec) - 16 kb single cycle 32-bit wide dual-ported sram, accessible as closely coupled data memory and instruction memory - 2 kb instruction cache and ahb memory- mapped spi flash read controller - 32 x 32 x 64 fast multiply - divide assist and saturation arithmetic - maskable interrupt aggregator/accelerator interface - maskable hardware wake-up events - sleep mode - jtag debug port, includes jtag master - mcu serial debug port - 8-channel dma interface supports smbus controllers and ec/host gp-spi controllers embedded flash - 192 kb user space + 2kb info block, 32-bit access, 35ns access time, 1 k cycles endurance - programmable by lpc, ec and jtag inter- faces - flash security enhancements C 4k boot block protection C direct jtag and direct lpc-protected (2) pages at or near top of memory for password protection legacy support - fast gatea20 & fast cpu_reset system to ec message interface - 8042 style host interface - embedded memory interface C host serial or parallel irq source C provides two windows to on-chip sram for host access C two register mailbox command interface C host access of virtual registers without ec intervention - mailbox registers interface C thirty-two 8-bit scratch registers C two register mailbox command interface C two register smi source interface - acpi embedded controller interface C four instances C 1 or 4 byte data transfer capable - acpi power management interface C sci event-generating functions battery backed resources - power-fail status register - 32 khz clock generator - week alarm timer inte rface with program- mable wake-up from 1ms to 45 days - vbat-powered control interface - vbat-backed 64 byte memory three ec-based smbus 2.0 host controllers - allows master or dual slave operation - controllers are fully operational on standby power - dma-driven i 2 c network layer hardware -i 2 c datalink compatibility mode - multi-master capable - supports clock stretching - programmable bus speeds - 400 khz capable - hardware bus access fairness interface - smbus time-outs interface - 8 x 3 x 3 port multiplexing peci interface 2.0 18 x 8 interrupt capable multiplexed keyboard scan matrix three independent hardware driven ps/2 ports - fully functional on main and/or suspend power - ps/2 edge wake capable 115 general purpose i/o pins - 8 gpio pass-through port (gptp) mec1609/mec1609i mixed signal mobile embedded flash arc ec bc-link/ vlpc base component downloaded from: http:///
mec1609/mec1609i ds00001769a-page 2 ? 2014 microchip technology inc. 3-pin led interface - programmable blink rates - breathing led output - operational in ec sleep state programmable 16-bit counter/timer interface - four wake-capable 16-bit auto-reloading counter/timer instances - four operating modes per instance: timer, one-shot, event and measurement. - 4 external inputs, 4 external outputs hibernation timer interface - two 32.768 khz driven timers - programmable wake-up from 0.5ms to 128 minutes system watch dog timer (wdt) input capture and compare timer - 32-bit free-running timer - six 32-bit capture registers - two 32-bit compare registers - capture, compare and overflow interrupts microchips multipoint vlpc tm serial intercon- nect bus master - forwards lpc transactions to vlpc periph- erals - forwards arc transactions to vlpc periph- erals bc-link tm interconnection bus - three high speed and one low speed bus masters controllers two general purpose serial peripheral interface controllers (ecgp-spi) - one 3-pin ec-driven full duplex serial com- munication interface - one 4-pin ec/host-driven full duplex serial communication interface to spi flash inter- face - flexible clock rates - spi burst capable spi flash read controller - 4 mb ahb memory-mapped address space - supports 2 kb ec instruction cache fan support - 8 programmable pulse-width modulator out- puts C multiple clock rates C 16-bit on & 16-bit off counters - four fan tachometer inputs - 6 x 2 capture/compare timer interface adc interface - 10-bit conversion in 10 s - 16 channels - integral non-linearity of 0.5 lsb; differen- tial non-linearity of 0.5 lsb two pin debug port with standard 16c550a reg- ister interface - accessible from host and ec - programmable input/output pin polarity inversion - programmable main power or standby power functionality - standard baud rates to 115.2 kbps, custom baud rates to 2 mbps resistor/capacitor id entification detection (rc_id) - single pin interface to external inexpensive rc circuit - replacement for multiple gpios - provides 8 quantized states on one pin integrated standby power reset generator clock generator - 32.768 khz-input clock - operational on suspend power - programmable clock power management control & distribution - 64.52 mhz 2% accuracy packages - 144 pin lfbga rohs compliant package - 144 pin tfbga rohs compliant package operating temperature - the mec1609 supports the commercial tem- perature range of 0 o c to +70 o c - the mec1609i supports the industrial tem- perature range of -40 o c to +85 o c downloaded from: http:///
? 2014 microchip technology inc. ds00001769a-page 3 mec1609/mec1609i description the mec1609/mec1609i is the mixed signal base component of a multi-device advanced i/o controller architecture. the mec1609/mec1609i incorporates a high-performance 32-bit arc 625 embedded microcontroller with a 192 kilo- byte embedded flash subsystem, 16 kilobytes of sram and 2 kilobytes of instruction cache with an ahb memory- mapped spi flash read controller. the mec1609 communicat es with the system host using the intel? low pin count bus. there are two distinct protocols that provide communication between the mec1609/mec1609i base component and companion components: bc-link ? and vlpc ? .bc-link ? in the mec1609/mec1609i can access up to four com- panion components. the bc-link ? protocol is peer-to-peer providin g communication between the mec1609/ mec1609i embedded controller and registers located in a companion. vlpc ? is a multi-drop pr otocol that matches the mec1609/mec1609i with up to three untrust ed companion components and one trusted companion component. the mec1609/me c1609i accepts lpc host (ich/pch) transac tions targeting blo cks internal to the mec1609/mec1609i and blocks physically located in vlpc ? companions. the arc 625 embedded microcontroller can also access blocks that are physically located in vlpc ? companion components. the mec1609/mec1609i is directly powered by two separa te suspend supply planes (vbat and vtr) and senses a third runtime power plane (vcc) to provide instant on and system power management functions. the mec1609/ mec1609i also contains an integrated vtr reset interf ace and a system power management interface that supports low-power states and can drive state changes as a resu lt of hardware wake events as defined by the mec1609/ mec1609i wake interface. the mec1609/mec1609i defines a software development syste m interface that includes an mcu serial debug port, a two pin serial debug port with a 16c550a register interface t hat is accessible to the ec or to the lpc host and can oper- ate up to 2 mb/s, a flexible flash pr ogramming interface and a jtag interface. the ec can also drive the jtag inter- face as a master. a top-level block diagram of t he mec1609/mec1609i is shown in figure 1: mec1609/mec1609i top-level block diagram on page 5 . an example of system level connection is shown in figure 2: example of mec1609/mec1609is connections to system components on page 6 . downloaded from: http:///
mec1609/mec1609i ds00001769a-page 4 ? 2014 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the bes t documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing co mmunications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data s heet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the version number, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur- rent devices. as device/doc umentation issues become known to us, we will publish an errata s heet. the errata will specify the revision of silicon and revision of document to which it applies. to determine if an errata sheet exis ts for a particular device, please check with one of the following: microchips worldwide web site; http://www.microchip.com your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include -literature number) yo u are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. downloaded from: http:///
? 2014 microchip technology inc. ds00001769a-page 5 mec1609/mec1609i block diagram figure 1: mec1609/mec1609i top-level block diagram cpu voltage analog vbat lad[3:0] lframe#, lreset#, pci_clk nsmi ser_irq, nclkrun xtal1 nreset_out vcc_pwrgd vr_cap jtag_rst# jtag_tdi jtag_tms jtag_clk uart_rx uart_tx 16550 (uart) debug port ` lpc interface & host interrupt interface jtag master and slave clock generation & pm i/f 32 khz crystal oscillator vbat ` legacy (fast_kb) port 92, cpu_reset, gatea20 kbrst* a20m* jtag_tdo vcc host configuration space access port configuration registers lpc access ec access arc 625 embedded controller (ec) subsystem jtag access system reset power control voltage regulator reset interface & power mux ps2_clk[2:0]* ecgp_sin led[2:0] msdata, msclk mcu debug port led controls gpio* general purpose i/o interface general purpose spi interface notes 1) all blocks powered by vtr except where noted. 2) signals with unique electrical requirements are highlighted. 3) asterisks (*) denote multiplexed signal functions. 64 byte memory vbat vbat alarm wake hibernation timer x2 wdt power fail reg vbat ecgp_sclk ecgp_sout embedded flash flash program- ming & securitty nfwp gptp-in[7:0], gptp-out[7:0] vtr vss 16-bit counter/ timers acpi pm msg i/f acpi ec msg i/f (x4) interrupt accelerator 16 k byte sram smbus interface pwm & fan tachometer interface fan_tach[3:0] (ict[3:0]) pwm[7:0] input capture compare timer xtal2 vcc 8042 host msg i/f smb0[7:0]_data*, smb1[2:0]_data*, smb2[2:0]_data* smb0[7:0]_clk*, smb1[2:0]_clk*, smb2[2:0]_clk* ps2_dat[2:0]* ps/2 interface bcm_dat[a:d] bcm_clk[a:d], bcm_int#[a:d] bc-link interface 1 ls-master 3 hs-masters vlpc interface vlpc_clk vlpc_data vlpc_frame kso[17:0] ksi[7:0] keyboard scan 8 channel dma analog data acquisition adc[15:0]* cpu voltage peci peci ready sb-tsi_clk sb-tsi_dat vref 2 kb cache rc_id analog rc_id flsclk, flsout, flsin,flscs# spi flash read controller flash spi peci_request# em i/f ict[5:4] mail- box reg- isters i/f downloaded from: http:///
mec1609/mec1609i ds00001769a-page 6 ? 2014 microchip technology inc. figure 2: example of mec1609/mec1609i ?s connections to system components mec1609/mec1609i ec 144 pin adc flash downloaded from: http:///
? 2014 microchip technology inc. ds00001769a-page 7 mec1609/mec1609i package outlines note: for the most current package drawings, see the microchip pa ckaging specification at http://www.microchip.com/packaging. figure 3: 144-pin lfbga 10x10x0.8 mm package outline (1.4 mm height) downloaded from: http:///
mec1609/mec1609i ds00001769a-page 8 ? 2014 microchip technology inc. figure 4: 144-pin tfbga 7x7x0.5 mm package outline (1.2 mm height) note: for the most current package draings, see the microchip packaging specification at http://.microchip.com/packaging downloaded from: http:///
? 2014 microchip technology inc. ds00001769a-page 9 mec1609/mec1609i appendix a: product brief revision history table a-1: revision history revision section/figure/entry correction ds00001769a (06-03-14) document release downloaded from: http:///
mec1609/mec1609i ds00001769a-page 10 ? 2014 microchip technology inc. the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site con- tains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), te chnical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of semi- nars and events, listings of microchip sales offi ces, distributors and factory representatives customer change notification service microchips customer notification service helps keep custom ers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisi ons or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under support, click on customer change notifi- cation and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this docu- ment. technical support is available through the web site at: http://www.microchip.com/support downloaded from: http:///
? 2014 microchip technology inc. ds00001769a-page 11 mec1609/mec1609i product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: mec1609, mec1609i temperature range: blank = 0 c to +70 c (extended commercial) i= - 4 0 c to +85 c (industrial) package: pzv = 144-pin tfbga pzp = 144-pin lfbga tape and reel option: blank = standard packaging (tray) tr = tape and reel (1) examples: a) mec1609-pzv 144-pin tfbga (7mm x 7mm, 0.5 pitch) rohs compliant package b) MEC1609-PZP 144-pin tfbga (10mm x 10mm, 0.8 pitch) rohs compliant package c) mec1609i-pzv industrial temperature, 144-pin tfbga (7mm x 7mm, 0.5 pitch) rohs compliant package d) mec1609i-pzp industrial temperature, 144-pin tfbga (10mm x 10mm, 0.8 pitch) rohs compliant package note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the dev ice package. check with your microchip sa les office for package availability with the tape and reel option. reel size is 4,000. part no. [x] xxx package temperature range device [x] (1) tape and reel option - - downloaded from: http:///
ds00001769a-page 12 ? 2014 microchip technology inc. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchips c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with y our specifications. microchip make s no representations or warranties of any kind whether ex press or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fi tness for purpose . microchip disclaims all liability arising fr om this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, i ndemnify and hold harmless microchip from any and all dama ges, claims, suits, or expenses resulting from such use. no licenses ar e conveyed, implic- itly or otherwise, under any micr ochip intellectual property rights. trademarks the microchip name and logo, the micr ochip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered tr ademarks of microchip technology incorporated in the u.s.a. a nd other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and t he embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, application maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z- scale are trademarks of microc hip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchi p technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. flexpwr, jukeblox, kleer, kleernet, medialb, and most the preceding is a non-exhaustive list of tra demarks in use in the us and other countri es. for a complete list of trademarks, e mail a request to legal.department@microchip.com . the absence of a trademark (name, logo, etc.) fr om the list does not constitute a waiver of any intellectual property rights that smsc has established in any of its trademarks. all other trademarks mentioned herein are pr operty of their respective companies. ? 2014, microchip technology incorporated, pr inted in the u.s.a., all rights reserved. isbn: 9781632762627 microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management system certified by dnv == iso/ts 16949 == downloaded from: http:///
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